PREFACE: Due to the COVID-19, I can not access the FPGA board in NetDB-Lab. So the vivado part will miss in the page until I go back to lab.
B. R. Wu and me have already done this project.
In this project, we implement JBF on FPGA. Using the unroll, pipeline, dataflow derivertives to accelerate the whole progress via vivado HLS. After
C simulation and C Synthesize. We export the IP core to vivado. And run the IP core which is faster than (600x) the original algorithm. The reasons of the high speed are not only the high parallel part, but also in spatial kernel, we use look-up table instead of computation.